CyberSecBulletin
CVE-2025-54520NVD status: Deferred

Kintex™ 7-Series FPGA: Improper Protection Against Voltage and Clock Glitches

CVE-2025-54520 is a high-severity improper protection against voltage and clock glitches vulnerability in Kintex™ 7-Series FPGA from AMD, with a CVSS 4.0 base score of 8.6 out of 10. It can be exploited with physical access to the device by an unauthenticated attacker, without any action from a user. Affected Kintex™ 7-Series FPGA versions: Refer to AMD-SB-8018. The record does not name a fixed version, so check the vendor advisory. There is no confirmed exploitation so far. EPSS estimates a 0.2% chance of exploitation within 30 days, which is low compared with other CVEs.

Next patch cycle

High severity with no evidence of exploitation so far.

What to do

  1. Check which version of Kintex™ 7-Series FPGA you run against the affected versions below, and install the vendor's latest release.

Affected products and versions

VendorProductAffected versionsFixed in
AMDKintex™ 7-Series FPGARefer to AMD-SB-8018Not stated
AMDArtix™ 7-Series FPGARefer to AMD-SB-8018Not stated

Version data comes from the organisation that assigned the CVE. Confirm against the vendor advisory before deciding you are unaffected.

How the severity score breaks down

Attack vector
PhysicalThe attacker must physically touch the device.
Attack complexity
LowNo special conditions are needed; the attack works reliably.
Attack requirements
NoneThe attack does not depend on a particular deployment or configuration.
Privileges required
NoneNo account or login is needed.
User interaction
NoneNo action by a victim is required.
Confidentiality (vulnerable system)
HighSerious loss of confidentiality on the vulnerable system.
Integrity (vulnerable system)
HighSerious loss of integrity on the vulnerable system.
Availability (vulnerable system)
HighSerious loss of availability on the vulnerable system.
Confidentiality (other systems)
HighSerious loss of confidentiality on systems beyond the vulnerable one.
Integrity (other systems)
HighSerious loss of integrity on systems beyond the vulnerable one.
Availability (other systems)
HighSerious loss of availability on systems beyond the vulnerable one.

Vector: CVSS:4.0/AV:P/AC:L/AT:N/PR:N/UI:N/VC:H/VI:H/VA:H/SC:H/SI:H/SA:H/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X. Scored by CNA (amd.com).

Official description

Improper Protection Against Voltage and Clock Glitches in FPGA devices, could allow an attacker with physical access to undervolt the platform resulting in a loss of confidentiality.

Source: the CVE record as published by its numbering authority, via NVD and CVE.org.

The underlying weakness: Improper Protection Against Voltage and Clock Glitches

The device does not contain or contains incorrectly implemented circuitry or sensors to detect and mitigate voltage and clock glitches and protect sensitive information or software contained on the device.

How developers prevent this class of flaw

  • A device needs to guard against fault attacks such as voltage glitches and clock glitches that an attacker may employ in an attempt to compromise the system. At the circuit-level, using Tunable Replica Circuits (TRCs) or special flip-flops such as Razor flip-flops helps mitigate glitch attacks. Working at the SoC or platform base, level sensors may be implemented to detect glitches. Implementing redundancy in security-sensitive code (e.g., where checks are performed)also can help with mitigation of glitch attacks.

More Improper Protection Against Voltage and Clock Glitches vulnerabilities (CWE-1247)

Timeline

  1. CVE record published.
  2. CISA published its SSVC assessment (exploitation: none, automatable: no, technical impact: total).
  3. Record last changed materially (score, affected products, status or references).

References

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