Improper Prevention of Lock Bit Modification
CWE-1231
The product uses a trusted lock bit for restricting access to registers, address regions, or other resources, but the product does not prevent the value of the lock bit from being modified after it has been set.
We track 2 vulnerabilities of this type. 100% are rated high or critical, and the average CVSS score is 7.7.
How this weakness is prevented
- Architecture and Design Implementation Testing: Security lock bit protections must be reviewed for design inconsistency and common weaknesses. Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.
Latest Improper Prevention of Lock Bit Modification vulnerabilities
- 7.5 High severity
AMD Ryzen™ Threadripper™ 3000 Processors: Improper Prevention of Lock Bit Modification
Improper input validation for DIMM serial presence detect (SPD) metadata could allow an attacker with physical access, ring0 access on a system with a non-compliant DIMM, or control over the Root of Trust for BIOS update, to bypass SMM isolation potentially re
- 7.8 High severity
NVIDIA DGX servers: Improper Prevention of Lock Bit Modification
DGX A100 SBIOS contains a vulnerability in the Pre-EFI Initialization (PEI)phase, where a privileged user can disable SPI flash protection, which may lead to denial of service, escalation of privileges, or data tampering.