Improper Handling of Faults that Lead to Instruction Skips

The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.

We track 1 vulnerability of this type. 100% are rated high or critical, and the average CVSS score is 9.8.

How this weakness is prevented

• Architecture and Design: Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.
• Architecture and Design: Design strategies for ensuring safe behavior if instructions attempt to be skipped.
• Architecture and Design: Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.
• Implementation: Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.
• Implementation: Use redundant operations or canaries to detect and respond to faults.