CyberSecBulletin
CVE-2023-32666NVD status: Deferred

4th Generation Intel(R) Xeon(R) Processors…: On-Chip Debug and Test Interface With Improper Access Control

CVE-2023-32666 is a high-severity on-chip debug and test interface with improper access control vulnerability in 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX, with a CVSS 3.1 base score of 7.2 out of 10. It can be exploited with local access to the system by an attacker with administrator privileges, without any action from a user. There is no confirmed exploitation so far. EPSS estimates a 0.15% chance of exploitation within 30 days, which is low compared with other CVEs.

Next patch cycle

High severity with no evidence of exploitation so far.

What to do

  1. Check which version of 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX you run against the affected versions below, and install the vendor's latest release.

Affected products and versions

Version data comes from the organisation that assigned the CVE. Confirm against the vendor advisory before deciding you are unaffected.

How the severity score breaks down

Attack vector
LocalThe attacker needs local access or must trick a user into running something.
Attack complexity
HighSuccess depends on conditions outside the attacker's control.
Privileges required
HighAdministrator-level access is required first.
User interaction
NoneNo action by a victim is required.
Scope
ChangedThe attack can reach beyond the vulnerable component into other systems.
Confidentiality
HighAll data handled by the component can be read.
Integrity
HighData or code can be modified at will.
Availability
NoneAvailability is not affected.

Vector: CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:H/I:H/A:N. Scored by CNA (intel.com).

Official description

On-chip debug and test interface with improper access control in some 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.

Source: the CVE record as published by its numbering authority, via NVD and CVE.org.

The underlying weakness: On-Chip Debug and Test Interface With Improper Access Control

The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface.

How developers prevent this class of flaw

  • If feasible, the manufacturer should disable the JTAG interface or implement authentication and authorization for the JTAG interface. If authentication logic is added, it should be resistant to timing attacks. Security-sensitive data stored in registers, such as keys, etc. should be cleared when entering debug mode.

More On-Chip Debug and Test Interface With Improper Access Control vulnerabilities (CWE-1191)

Timeline

  1. CVE record published.
  2. CISA published its SSVC assessment (exploitation: none, automatable: no, technical impact: total).
  3. Record last changed materially (score, affected products, status or references).

References

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