Intel(R) Xeon(R) 6 processor with Intel(R) TDX: Improper Handling of Overlap Between Protected Memory Ranges
CVE-2025-22889 is a high-severity improper handling of overlap between protected memory ranges vulnerability in Intel(R) Xeon(R) 6 processor with Intel(R) TDX, with a CVSS 3.1 base score of 7.9 out of 10. It can be exploited with local access to the system by an attacker with administrator privileges, without any action from a user. Affected Intel(R) Xeon(R) 6 processor with Intel(R) TDX versions: See references. The record does not name a fixed version, so check the vendor advisory. There is no confirmed exploitation so far. EPSS estimates a 0.17% chance of exploitation within 30 days, which is low compared with other CVEs.
High severity with no evidence of exploitation so far.
What to do
- Check which version of Intel(R) Xeon(R) 6 processor with Intel(R) TDX you run against the affected versions below, and install the vendor's latest release.
Affected products and versions
| Vendor | Product | Affected versions | Fixed in |
|---|---|---|---|
| Intel(R) Xeon(R) 6 processor with Intel(R) TDX | Intel(R) Xeon(R) 6 processor with Intel(R) TDX | See references | Not stated |
Version data comes from the organisation that assigned the CVE. Confirm against the vendor advisory before deciding you are unaffected.
How the severity score breaks down
- Attack vector
- LocalThe attacker needs local access or must trick a user into running something.
- Attack complexity
- LowNo special conditions are needed; the attack works reliably.
- Privileges required
- HighAdministrator-level access is required first.
- User interaction
- NoneNo action by a victim is required.
- Scope
- ChangedThe attack can reach beyond the vulnerable component into other systems.
- Confidentiality
- HighAll data handled by the component can be read.
- Integrity
- HighData or code can be modified at will.
- Availability
- NoneAvailability is not affected.
Vector: CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N. Scored by CNA (intel.com).
| Scoring system | Score | Severity | Scored by |
|---|---|---|---|
| CVSS 4.0 | 7.0 | High | CNA (intel.com) |
| CVSS 3.1 | 7.9 | High | CNA (intel.com) |
Official description
Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processor with Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.
Source: the CVE record as published by its numbering authority, via NVD and CVE.org.
The underlying weakness: Improper Handling of Overlap Between Protected Memory Ranges
The product allows address regions to overlap, which can result in the bypassing of intended memory protection.
How developers prevent this class of flaw
- Ensure that memory regions are isolated as intended and that access control (read/write) policies are used by hardware to protect privileged software.
More Improper Handling of Overlap Between Protected Memory Ranges vulnerabilities (CWE-1260)
Timeline
- CVE record published.
- CISA published its SSVC assessment (exploitation: none, automatable: no, technical impact: total).
- Record last changed materially (score, affected products, status or references).
References
Other references
Recent Improper Handling of Overlap Between Protected Memory Ranges vulnerabilities
- 7.5 High severity
- 9.8 Critical severity
- 8.2 High severity
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